1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, one having a redundancy memory cell and an improvement of its means for remedying a defective memory.
2. Description of the Related Art
In the existing semiconductor memory device not only normal access is gained to a memory but also a defective memory cell is remedied by replacing the defective memory cell.
FIG. 8 is a block diagram showing the arrangement of an existing semiconductor memory having the aforementioned redundancy memory cells. The memory in FIG. 8 is divided into four memory arrays MCA's. In addition to column decoders CD, row decoders RD and sense amplifiers SA, one row of redundancy memory cells R is provided for each of the memory cell arrays. X denotes row addresses input to the row decoder RD and Y denotes column addresses input to the column decoder CD.
In this case, means is provided for replacing any defective memory cell by a redundancy memory cell. Replacement is carried out by programming the column address of any defective memory cell in a programmable decoder PDC provided relative to the memory cell in question.
FIG. 9 is a circuit diagram of an example of a programmable decoder PDC shown enclosed by a broken line in FIG. 8. One input of each of NAND gates 200, 201, 202 and 203 is initially controlled, by a corresponding one of fuses F0, F1, F2 and F3, on the basis of address information of a corresponding defective cell. A corresponding column address line is connected to the other input of the respective NAND gate. The outputs of the NAND gates 200, 201, 202, and 203 are supplied to a 4-input AND gates 205 and, upon receipt of 10 a column address of any defective memory cell, the AND gate 205 inhibits the selection of a normal memory cell and delivers a redundancy memory cell select signal RSL to a redundancy memory cell select line, not shown.
In recent years, high integration density has been achieved in memory devices involving a larger number of divided memory cell arrays. Therefore, high integration density cannot be achieved if the memory cell arrays as shown in FIG. 8 are adopted. As a countermeasure, a plurality of memory cell arrays are arranged so as to share a column decoder or row decoder or both.
FIG. 10 shows an example of the arrangement of an existing semiconductor memory where a plurality of memory cell arrays share a column decoder. In this arrangement, row decoders RD, sense amplifiers SA, and a row of redundancy memory cells RM are arranged for the memory cell arrays MCA, and all the memory cell arrays share a single column decoder CD.
In the aforementioned arrangement, the replacement of a defective memory cell by a corresponding redundant memory cell is implemented through the initial programming of the column address of the defective memory cell. The programmable decoder PDC has an arrangement such as that shown in FIG. 9. Specifically, the column address line is connected to the programmable decoder and, upon receipt of a column address corresponding to any defective memory cell, the decoder inhibits the selection of any normal memory cell and delivers a corresponding redundancy memory cell select signal.
In the arrangement shown in FIG. 10, however, a lower percentage of defective memory cell replacement is expected as compared with the arrangement shown in FIG. 8. Let it be assumed that memory cells each having different column addresses are defective in each of the memory arrays. In the arrangement shown in FIG. 8, as a remedial measure for the defective memory cell, the column address corresponding to the defective memory cell is programmed for the programmable decoder PDC provided relative to the memory cell array, whereby it is possible to replace the respective defective memories. In the arrangement shown in FIG. 10, only one programmable decoder PDC is provided for storing the column addresses of the defective memory cells, failing to remedy the aforementioned defects.
Since only the column address of one defective memory cell is programmed in the programmable decoder in the case where the respective cell arrays share the column decoder, there is a drop in the remedial percentage of defective memory cells. In order to cope with this problem, a plurality of programmable decoders may be prepared, in which case the defective memory cells of the memory cell arrays at different column addresses can be replaced through a logical operation between the output of the programmable decoder and a memory cell array select signal.
FIG. 11 is an example of the aforementioned arrangement in which four programmable decoders PD0, PD1, PD2, and PD3 are prepared and the defective memory cells of the memory cell arrays at different column addresses can be replaced by connecting the output of the programmable decoder to a portion of the row address.
Let it be assumed that in the arrangement of FIG. 11, 4-bit row addresses (X0, X1, X2, X3) and 2-bit column addresses (Y0, Y1) are entered and access is gained to one memory cell. A semiconductor memory in FIG. 11 is divided into four memory cell arrays MCA0, MCA1, MCA2, and MCA3 and the 2-bit row addresses (X2, X3) are employed to select a memory cell array to be accessed. The remaining 2-bit row addresses (X0, X1) are connected to row decoders RD0, RD1, RD2, and RD3 and used to select a row select line in the memory cell array. Further, the column addresses (Y0, Y1) are connected to the column decoder CD and used to select a column select line.
FIG. 12 is a circuit diagram of a connection arrangement of four programmable decoders PD0, PD1, PD2, and PD3 shown enclosed by a broken line in FIG. 11. These programmable decoders are the same in arrangement as the programmable decoder shown in FIG. 9, and their outputs are supplied to the first inputs of 3-input AND gates 300, 301, 302, and 303, respectively. In order to perform respective predetermined operations, the AND gates 300, 301, 302, and 303 are logically combined using the aforementioned 2-bit row addresses (X2, X3), and their outputs are connected to a 4-input OR gate 305. The OR gate 305 delivers a redundancy memory cell select signal RSL as an output and is coupled to a redundancy memory cell select line (not shown) in the column decoder.
The column addresses (Y0, Y1) and row addresses (x2, X3) for selecting a corresponding memory cell array are input to the respective programmable decoders PD0, PD1, PD2, and PD3. By so doing, the column address of any defective memory cell in the corresponding memory cell array is programmed in the corresponding programmable decoder.
Here, let it be assumed that the memory cell arrays, 1, 2, 3, and 0 correspond, as the column addresses of defective memory cells, to MCA0, MCA1, MCA2, and MCA3, respectively. In this case, 1, 2, 3 and 0 are programmed in the programmable decoders PD0, PD1, PD2, and PD3, respectively. This program is achieved by blowing out the corresponding fuses F0, F1, F2, and F3. FIG. 13 shows cut-off spots of the respective fuses.
FIG. 14 is a schematic diagram showing signal paths for the replacing of defective memory cells in the arrangement shown in FIG. 12. In the arrangement shown in FIG. 14, column addresses (Y) are input to corresponding programmable decoders. In the case of a semiconductor memory such as a DRAM, in which addresses are multiplexed, normally the row address (X) is input first and then the column address (Y) is input.
A critical path for obtaining a redundancy memory cell select signal RSL after the inputting of the address corresponds to a signal path run through a logic operation circuit LOP from the programmable decoder PDC indicated by a broken line in FIG. 14.
In the logic operation of a signal delivered from the respective programmable decoders in the arrangement shown in FIG. 12, there is a time delay from the inputting of the column address to the determination of the selection of a redundancy memory cell select line. This time delay cannot be ignored if the number of divided memory cells is increased.
In addition to the aforementioned conventional examples, other practical arrangements may be considered as programmable decoders. Since, however, the column addresses are connected to the inputs of respective programmable decoders, there is a time delay until a redundancy memory cell select signal is finally obtained after a logic operation has been performed past the programmable decoder subsequent to the inputting of the column address.
To alleviate this problem, the logic operation on the output of the programmable decoder may be performed in a cascade-connected configuration. However, in this case, a parasitic capacitance on the node of the cascade connection is increased due to an increase in the number of programmable decoders. Therefore, the cascade connection of logic circuits for logic operation on their outputs does not result in a shortening of the time from the inputting of the column address to the outputting of the redundancy memory cell select signal.
Due to the current trend toward higher integration density of existing semiconductor memories, the circuit arrangement high in a remedial percentage of defective memory cells becomes complex and, due to an increase in the number of divided memory cells involved, the time until a redundancy memory cell select signal is output increases.
The present invention has been developed taking the above-mentioned factors into consideration, and its object is to provide a semiconductor memory device which, even thought it contains a plurality of divided memory cell arrays, can replace defective memory cells with minimum delay and replace a high percentage of defective cells.